Standard cell height for semiconductor devices is conventionally an integer times the pitch of the second metal routing track (M2 pitch), such as an 8 track library or a 10 track library. Denser track libraries, such as the 8 track library, provide for better scaling but also impose significant design challenges, particularly on middle of line (MOL) constructs. Further, for FinFET semiconductor devices, the M2 pitch is usually different from the fin pitch so that a cell height that is a multiple of the M2 pitch results in a non-uniform fin grid.
A need therefore exists for a cell height that is a non-integer multiple of the M2 pitch, such as an 8.25 track, and the resulting device.